1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to on-chip mechanisms for regulating the power supply voltage of an integrated circuit.
2. Description of the Prior Art
The use of increasingly small process geometries and increasingly rapid clock frequencies have exacerbated the inductive (Ldi/dt) supply noise within integrated circuits. This impacts the robustness of power supply delivery networks. Inductive supply noise is further aggravated by otherwise desirable power reduction techniques, such as power/clock-gating and frequency-stepping in dynamic voltage scaling systems. On-chip passive decoupling capacitance, which has traditionally been used for suppressing inductive supply noise, has become increasingly disadvantageous due to its area and leakage power overhead. As a result, several circuit techniques have been proposed to actively regulate the power supply against sudden surges in load/current. These proposed techniques suffer from various disadvantages, such as delivering a limited charge, being suited only for resonance suppression or requiring an additional high voltage supply. Examples of these techniques can be found in Ang et al., “An on-chip voltage regulator using switched decoupling capacitors,” ISSCC Dig. Tech. Papers, pp. 438-439,2000, Xu et al.; “On-die supply-resonance suppression using band-limited active damping” ISCC Dig. Tech. Papers, pp. 268-269, 2007; and Nakamura et al., “An on-chip noise canceller with high voltage supply lines for nanosecond-range power supply noise,” Symp. VLSI Circuits, pp. 124-125, 2007.